Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool
- Autores:
-
Castano-Londono L.
Alzate Anzola C.
Marquez-Viloria D.
Gallo G.
Osorio G.
- Tipo de recurso:
- Fecha de publicación:
- 2019
- Institución:
- Instituto Tecnológico Metropolitano
- Repositorio:
- Repositorio ITM
- Idioma:
- OAI Identifier:
- oai:repositorio.itm.edu.co:20.500.12622/3219
- Acceso en línea:
- http://hdl.handle.net/20.500.12622/3219
- Palabra clave:
- Rights
- License
- http://purl.org/coar/access_right/c_14cb
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Castano-Londono L.Alzate Anzola C.Marquez-Viloria D.Gallo G.Osorio G.2020-08-28T22:27:41Z2020-08-28T22:27:41Z2019http://hdl.handle.net/20.500.12622/321910.1007/978-3-030-31019-6_5Scopushttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85075682082&doi=10.1007%2f978-3-030-31019-6_5&partnerID=40&md5=0beb63940830a14de3ca0507f94350a5Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis ToolCommunications in Computer and Information Scienceinfo:eu-repo/semantics/conferenceObjecthttp://purl.org/coar/version/c_970fb48d4fbd8a85http://purl.org/coar/resource_type/c_c94f10525263http://purl.org/coar/access_right/c_14cbPublication20.500.12622/3219oai:dspace-itm.metabuscador.org:20.500.12622/32192025-06-20 16:15:51.995metadata.onlyhttps://dspace-itm.metabuscador.orgRepositorio Instituto Tecnológico Metropolitano de Medellínbdigital@metabiblioteca.com |
| dc.title.spa.fl_str_mv |
Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool |
| dc.title.alternative.none.fl_str_mv |
Communications in Computer and Information Science |
| title |
Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool |
| spellingShingle |
Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool |
| title_short |
Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool |
| title_full |
Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool |
| title_fullStr |
Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool |
| title_full_unstemmed |
Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool |
| title_sort |
Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool |
| dc.creator.fl_str_mv |
Castano-Londono L. Alzate Anzola C. Marquez-Viloria D. Gallo G. Osorio G. |
| dc.contributor.author.none.fl_str_mv |
Castano-Londono L. Alzate Anzola C. Marquez-Viloria D. Gallo G. Osorio G. |
| publishDate |
2019 |
| dc.date.issued.none.fl_str_mv |
2019 |
| dc.date.accessioned.none.fl_str_mv |
2020-08-28T22:27:41Z |
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2020-08-28T22:27:41Z |
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info:eu-repo/semantics/conferenceObject |
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http://purl.org/coar/version/c_970fb48d4fbd8a85 |
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http://purl.org/coar/resource_type/c_c94f |
| dc.identifier.uri.none.fl_str_mv |
http://hdl.handle.net/20.500.12622/3219 |
| dc.identifier.doi.none.fl_str_mv |
10.1007/978-3-030-31019-6_5 |
| url |
http://hdl.handle.net/20.500.12622/3219 |
| identifier_str_mv |
10.1007/978-3-030-31019-6_5 |
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1052 |
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52 |
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63 |
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Scopus |
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Instituto Tecnológico Metropolitano |
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https://www.scopus.com/inward/record.uri?eid=2-s2.0-85075682082&doi=10.1007%2f978-3-030-31019-6_5&partnerID=40&md5=0beb63940830a14de3ca0507f94350a5 |
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Repositorio Instituto Tecnológico Metropolitano de Medellín |
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bdigital@metabiblioteca.com |
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1837096907888918528 |