APA (7th ed.) Citation

(2019). Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool.

Chicago Style (17th ed.) Citation

Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool. 2019.

MLA (8th ed.) Citation

Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool. 2019.

Warning: These citations may not always be 100% accurate.