Desing of a Network-On-Chip platform for MPSoCS using TLM 2.0 standard and FPGA implementation (2011)
Complex systems that include a great variety of modules inside the same dice require higher level design techniques that allow obtaining accurate models suitable to test hardware as well as software at early stages; multiprocessors Systems On-Chip (MPSoCs) are scaling to levels where it is possible to embed tens and up to hundreds of cores on the same chip. Such architectures cannot be integrated with traditional bus structures as they are not scalable; as a solution to that, a new paradigm called Network on Chip (NoC) has gained strength to solve this issue. System C, an IEEE standard for electronic level design (ESL) is used here to build a NoC functional model; to simplify hardware details and speed up simulations, the new Transaction Level Modelling standard (TLM 2.0) is also adopted. Relying on different design constrains, variables such as router and network interfaces architectures, routing algorithms, message and flit size, etc., are evaluated. At a final stage, a VHDL synthesis is done and compared with other implementations. Results prove this design flow to be adequate and helpful for this kind of systems due to its size and complexity.